A dynamic memory typically has four basic memory cycles including a read, a write, a read-modify-write and a refresh cycle. An oscillator circuit is commonly used to provide a refresh request signal at a frequency which is adequate to refresh the memory. A refresh request signal for refreshing memory may occur asynchronously with respect to the time during which a non-refresh cycle is requested. Upon receiving the refresh request signal, the memory circuit must be capable of deciding whether to perform a memory cycle such as a read or a write or to refresh the memory. In order to arbitrate between refresh cycles and memory cycles, a storage device is typically needed to store the decision. However, due to the asynchronous nature of the signals, the set-up time of the storage device may be violated causing the storage device to enter an indeterminate or metastable state. Operation of a storage device in the metastable state results in the storage device oscillating or becoming otherwise unfunctional for a period of time depending upon the type of storage device. Therefore, a time delay is designed into the circuit to provide time for the storage device to settle. Previous memory circuits have utilized arbiters which require the arbitration time to be at the beginning of each memory cycle. As a result, during the beginning of each memory cycle, the memory circuit is not being accessed and thus not efficiently utilized.